Before we proceed further, you may want to take a moment to reflect on the stuff we’ve looked at thus far to see of you can spot the problem. The only problem, as I mentioned before, is that my chum made a small error. All we have to do is wire the D0 to D7 inputs to the 0s and 1s we wish to appear on the Q output as illustrated by the desired truth table. Basically, we can use our 8:1 multiplexer to implement any 3-input logical function.
![multisim 14.1 bcd to 7 segment display decoder pin out multisim 14.1 bcd to 7 segment display decoder pin out](https://www.electronicshub.org/wp-content/uploads/2014/03/BCD-to-7-segment-Decoder-Design-Using-Basic-Gates.jpg)
What he’s done is to hard-wire the D0 to D7 inputs to the 0 and 1 values corresponding to the Q output from our original truth table as illustrated below: Now, take a moment to refer back to my chum’s implementation. If we ignore the INH and !OE signals for the moment, we can represent the functionality of the remainder of the chip as a cascade of 2:1 multiplexers as illustrated below: CD4512 core functionality envisioned as a cascade of 2:1 multiplexers (Source: Max Maxfield) Meanwhile, a 1 on the active-low !OE (“output enable” I can’t draw the bar over this signal in this text) will disable the output and cause it to enter a high-impedance (Z) state. A 1 on the active-high INH (“inhibit”) will force the output to a 0. We also see that there are two additional control pins. Whatever logic value is on the selected input will be presented on the Q output. The three selection inputs, A, B, and C are used to select one of the eight D0 to D7 data inputs. What this tells us is that the CD4512 is an 8:1 multiplexer. The following is my interpretation of the data sheet’s truth table with the pin names slightly modified to match the chip diagram shown above: CD4512 truth table (Source: Max Maxfield) I wasn’t au fait with the CD4512 off the top of my head, so I had a quick Google while no one was looking and located this data sheet.
![multisim 14.1 bcd to 7 segment display decoder pin out multisim 14.1 bcd to 7 segment display decoder pin out](https://media.cheggcdn.com/study/b80/b808148e-d5cb-4dc2-b9fd-7a5fdaee57cd/image.png)
We will discuss this slipup in a moment, but first let’s look at the diagram he sent me: Note that this is an INCORRECT implementation (Source: Max Maxfield) I was going to mention my chum’s name here (he gave me his permission), but I decided to withhold it because he made an eensy-weensy mistake. This message was accompanied by diagram shown below. All you need to do is connect the eight inputs to GND (Ground) or VDD to match the 0s and 1s of the Q output of the truth table. It uses a CD4512, which has A, B, and C inputs that selects one-of-eight data inputs (D0 to D7) and presents the state of the selected input on the Q output. It will work for any logic combination of the three inputs, and it’s easy to go from the truth table to the circuit diagram. Attached is a one-chip solution to the PCB Etching Tank problem.
![multisim 14.1 bcd to 7 segment display decoder pin out multisim 14.1 bcd to 7 segment display decoder pin out](https://s3.studylib.net/store/data/008891754_1-894e61b6c6a84102df460845f75ceda7.png)
Hi Max, I enjoyed your “Logic Gates, Truth Tables, and Karnaugh Maps, Oh My!” article. I thought we’d put this to sleep, until a chum of mine sent me the following message:
![multisim 14.1 bcd to 7 segment display decoder pin out multisim 14.1 bcd to 7 segment display decoder pin out](http://1.bp.blogspot.com/-PfyW-bk10Bs/T0Sa6aitaJI/AAAAAAAAAIE/SMa4fVSavyU/s1600/扫描0004.jpg)
The bottom line is that we ended up with the following truth table:įrom this, using the Karnaugh map minimization techniques discussed in my aforementioned column, we ended up with the following logic circuit and Boolean equation: (Source: Max Maxfield) You can find the original posting by clicking here. Recently, I penned a column Logic Gates, Truth Tables, and Karnaugh Maps, Oh My! In this column we discussed a PCB Etching Tank logic problem that a student had posted to the EEWeb Forums. On the other hand, these problems can “keep on giving” when it comes to their ability to teach us things. On the one hand, some logic problems never seem to go away. It’s possible to use an 8:1 multiplexer to implement any 3-input logical function, but can we use it to implement a 4-input function?